Digital demodulators in modern technology require operating at higher reduced sampling rates across a wide range of bandwidths in a satellite QPSK receiver. In multi channel per carrier (MCPC), multiple channels of programs are muxed in one QPSK signal spectrum across a bandwidth of a satellite transponder at a high symbol rate. In single channel per carrier (SCPC), each QPSK spectrum has just one channel of program where individual carriers are spread across a bandwidth of a satellite transponder that sample data at a low symbol rate. The process of converting a signal from a given rate to a reduction in sampling rate is know as decimation or down sampling.
In FIG. 1, there is shown a satellite QPSK receiver with a digital QPSK demodulator having an antenna I detecting a radio frequency (RF) signal, typically in the Ku band. A tuner 2 receives the RF signal and transmits an intermediate frequency that has been translated, for example, to 479.5 MHz, to scalars 3 and 4. A local oscillator 5 is coupled to the scalars 3 and 4 for sending the signals to a dual analog-to-digital (ADC) converter 6. The dual ADC converter 6 is driven by a fixed frequency crystal oscillator 7 with a fs sampling rate, typically at a frequency of greater than 60 MHz. The dual ADC converter 6 transmits a quadrature ("Q") signal and an in-phase ("I") signal to the digital QPSK demodulator 8.
FIG. 2 is a block diagram of a conventional digital QPSK demodulator 8 receiving the I and Q signals from the ADC converter 6. A typical interpolator 9 has two input arms, I and Q, of finite impulse response (FIR) filters (not shown) sharing the same time-varying filter coefficients generated from a look-up table. The FIR interpolation filters include shift registers for storing the asynchronous input data. A symbol timing NCO 10 provides the synchronous timing phase so that the FIR interpolation filters can access a coefficient look-up table to obtain a set of filter coefficients. The interpolator 9 re-samples the asynchronous input data based on the filter coefficients and performs mathematical computations to produce synchronized output signals.
A half-Nyquist filter 11 also contains two input arms, I and Q, coupled to a complex multiplier 12. The half-Nyquist filter 11 typically performs the computation of a "square root raised cosine" filter (not shown) for matching with a spectrum shaping filter from the transmission end which is also represented by a "square root raised cosine" filter. The half-Nyquist filter 11 filters out undesirable signals including the out-of-band noise and signal interference injected by adjacent channels. A conventional implementation of the half-Nyquist filter 11 uses a FIR filter which operates at the rate of two samples per symbol, that is, 2/T where T denotes the symbol duration.
The demodulated signals produced by the half-Nyquist filter 11 should preferably be free of any carrier error. Before Q and I signals are fed into the half-Nyquist filter 11, the complex multiplier 12 is coupled in front of the half-Nyquist filter 11 for correcting any carrier errors. After the demodulated signals are generated from the half-Nyquist filter 11, a carrier discriminator 13 is coupled to the output of the half-Nyquist filter 1 1 to estimate the carrier error in the demodulated signals. The carrier discriminator 13 sends the estimated carrier error to a carrier loop filter 14 to control the oscillation of a carrier NCO 15, a numerically controlled oscillator. The carrier NCO 15 generates a complex sinusoid tone of the form: cos(.DELTA..omega.n+.DELTA..theta.)-j * sin(.DELTA..omega.n+.DELTA..theta.), where the symbol .DELTA..omega. denotes the carrier frequency error and the symbol .DELTA..theta. denotes the carrier phase error. In computing a complex number in the form of (I+jQ) * (cos+jsin), the complex multiplier 12 multiplies the I signal, which represents a real part of the complex number, and the Q signal, which represents an imaginary part of the complex number, by the complex sinusoid tone of cos(.DELTA..omega.n+.DELTA..theta.)-j * sin(.DELTA..omega.n+.DELTA..theta.) to produce a product value that is free of carrier error. The complex multiplier 12, the carrier discriminator 13, the carrier loop filter 14, and the carrier NCO 15 combine to form a phase-lock loop for carrier synchronization.
Similar to the carrier synchronization, a symbol timing synchronization of a phase-lock loop is formed from the combination of the interpolator 9, a symbol timing discriminator 16, a symbol timing loop filter 17, and the symbol timing NCO 10. One difference between the carrier synchronization and the symbol timing synchronization is that the symbol timing NCO 10 does not generate oscillating complex tone but rather the symbol timing NCO 10 generates periodic timing phases, indicating the locations of the synchronous data samples in the sequence of an asynchronous input data.
A conventional FIR interpolator, such as the interpolator 9, is typically limited to an interpolation rate of at least a one-half ratio between the output rate verses the input rate. If the interpolator 9 is required to interpolate data at less than a one-half ratio, the out-of-band noise spectral component will be aliased into the desired spectral range, rendering the interpolator 9 unable to accurately interpolating the data. For example, if the input rate from ADC 6 to the interpolator 9 is at 60 mega samples per second, then the maximum output rate is typically limited to at least 30 mega samples per second. Thus, the demodulator 8 as shown in FIG. 2 cannot operate at a symbol rate of less than a one-quarter ratio of the sampling rate from ADC 6. A conventional solution to resolve the one-half sampling rate limitations of an interpolator is to couple a decimator (not shown) in front of an interpolator. The decimation rate of the decimator, with a base power of two, is chosen so that the range of the interpolation rate is between 1/2 to 1.
In FIG. 3a, there is shown a conventional schematic circuit of a single-input-single-output ("SISO") programmable down-sampler. A two-fold decimator 18 receives an I or Q signal at an input data rate denoted by a symbol R. The output of the two-fold decimator 18 is decimated by a factor of two and the output rate is computed at R/2. The two-fold decimator 18 is cascaded to a two-fold decimator 19 to decimate by a factor of four and generates an output rate at R/4. The two-fold decimator 19 is further cascaded to a two-fold decimator 20 to decimate by a factor of eight and generates an output rate at R/8. A selector 21 receives a select control signal that determines which inputs to activate, either no decimation, decimation by a factor of two, decimation by a factor of four, or decimation by a factor of eight, to generate an output I or Q signal. A dual SISO programmable down-sampler can be used to implement a two-inputs-two-outputs programmable down-sampler. FIG. 3b shows an equivalent representation of the two-fold decimator 18 that contains a low pass filter (LPF) 22 and a down-sampler by two 23. The LPF 22 can be implemented as a half-band filter, with the coefficients of the half-band filter in the sequence of {. . . , 0, h(-5), 0, h(-3), 0, h(-1), h(0), h(1), 0, h(3), 0, h(5), 0, . . . }, where h(-n)=h(n) and h(2n)=0 for any non-zero integer n.
The conventional polyphase two-fold decimator operates at one-half of the input rate, denoted by R/2, but supports only single-input-single-output computation. In order to compute both the output signals of I and Q, two SISO polyphase decimators are required, which would require two sets of hardware including twice the number of multipliers and adders.
Accordingly, it is desirable to have a programmable down-sampler that re-samples data at a variable-rate below the one-half sampling rate. It is also desirable to have a programmable down-sampler that computes I and Q signals in more integrated and reduced dimensions.